1) Field of the Invention
The present invention relates to a multi-row wiring member for semiconductor device for achieving flip-chip mounting of semiconductor elements thereon and a method for manufacturing the same.
2) Description of Related Art
Conventionally, of substrates for semiconductor devices, there are those of a type intended to complete a semiconductor device by peeling off a base material thereof after mounting a semiconductor element thereon and sealing the entirety with a resin, as described in Japanese Patent Application Laid-Open No. 2015-185619.
As shown in FIG. 5A, the substrate for semiconductor device described in JP Patent Application Laid-Open No. 2015-185619 is provided, on a base material 51 made of a stainless steel material or the like, with a semiconductor-element mounting portion 52a and terminal portions 52b, both of which are formed of a metal plating layer. Each of the terminal portions 52b is formed to have an internal terminal face 52b1 and an external terminal face 52b2 in a back-to-back arrangement.
On the semiconductor-element-mounting side of each of the semiconductor-element mounting portion 52a and the terminal portions 52b, an overhang 52a1 or 52b3 is formed around the upper edge thereof. On the base-material side of the semiconductor element mounting portion 52a and the terminal portions 52b, a thin film made of Au or the like is formed by plating so that the external terminal faces assure appropriate soldering in mounting of a semiconductor device to be manufactured.
Manufacturing of a semiconductor device upon use of the substrate for semiconductor device of FIG. 5A is conducted through mounting a semiconductor element 53 on the semiconductor-element mounting portion 52a, connecting electrodes of the semiconductor element 53 and the terminal portions 52b with wires 54, forming a sealing resin portion 55 by sealing the side where the semiconductor element 53 is mounted, and then peeling off the base material 51, to complete a semiconductor device (see FIGS. 5B-5D).
Also, conventionally, of substrates for semiconductor device, there are those of a type in which internal terminals, external terminals and wiring portions are formed by metal plating on a metal sheet, to be used for a semiconductor device with BGA (Ball Grid Array) structure, as described in Japanese Patent Application Laid-Open No. 2009-164594.
The substrate for semiconductor device described in JP Patent Application Laid-Open No. 2009-164594 is configured, as shown in FIG. 6A, so that, on a metal sheet 61 as a base material, formed is an external-terminal-side plating layer having external terminal portions 62, on which formed with a same shape as the external-terminal-side plating layer is an intermediate layer 63, on which further formed with the same shape as the intermediate layer 63 is an internal-terminal-side plating layer having internal terminal portions 64. This substrate for semiconductor device is configured so that the surface of the internal-terminal-side plating layer having internal terminal portions 64, which are to achieve electrical connection with a semiconductor element, is to be an uppermost surface and so that the height from the metal sheet to the uppermost surface is substantially uniform over the entirety.
In manufacturing a semiconductor device, the substrate for semiconductor device described in JP Patent Application Laid-Open No. 2009-164594 is used with a metal-sheet-side surface of the external-terminal-side plating layer being in contact with a surface of the metal sheet as external terminal faces and a farther surface of the internal-terminal-side plating layer in reference to the metal sheet being uncovered as internal terminal faces. To be specific, the following steps are to be performed; mounting a semiconductor element 65 on the internal-terminal-face side of the substrate for semiconductor device and fix it with an adhesive layer 66, connecting electrodes of the semiconductor element and internal terminal portions 64 with wires 67, forming a sealing resin portion 68 by sealing the entirety with a resin, and removing the metal sheet by dissolving it by means of etching or the like so that the back surface of the sealing resin is made uncovered along with faces of the external-terminal-side plating layer having the external terminal portions 62. After that, the following steps are to be performed; forming a solder resist layer 69 covering the entire surface of the uncovered external-terminal-side plating layer, forming openings 70 that uncovers the external terminal portions 62 alone (see FIGS. 6B-6E), and embedding solder balls into the openings 70 at which the external terminal portions 62 are uncovered, to connect the external terminal portions 62 with external equipment (see FIG. 6F).
Since the external-terminal-side plating layer having external terminal portions 62, the intermediate layer 63 and the internal-terminal-side plating layer having internal terminal portions 64 are overlaid one on another to have a same shape so that wiring portions are formed between the internal terminal portions 64 and the external terminal portions 62, the pitch of the internal terminals and the external terminals is adjustable in accordance with a design of the wiring portion in the substrate for semiconductor device described in JP Patent Application Laid-Open No. 2009-164594.
The inventors of the present application, upon repeated trial and error at the stage before introducing the present invention, have devised a wiring member for semiconductor device that enables manufacturing of a highly-reliable resin-sealed semiconductor device through a reduced number of steps and a manufacturing method for the same wiring member; the wiring member enables reduction in thickness and size of the semiconductor device, improves adhesion between a plating film that forms terminal portions and a resin, achieves uniform height of a surface of the internal-terminal-side plating layer on which the semiconductor element is to be mounted and internal terminal portions to be electrically connected with the semiconductor element, eliminates, in the manufacturing process for the semiconductor device, the step of removing the metal sheet by etching and the step of forming openings that uncover external terminal portions alone, and moderating a warpage of the sealing resin as cured.
As a result of further study and consideration, the inventors of the present application have found that this prototypal wiring member for semiconductor device and the method for manufacturing the same as devised involved problems to be improved for mass-production of semiconductor devices.